module RegIfId (
    
    
    input [31:0] pc_in,
    input [31:0] instr_in,
    input PcSrc,
    input stall,
    input clk,
    output reg [31:0] pc_out,
    output reg [31:0] instr_out
    
);
   
    always @(posedge clk) begin
        if(!stall)
        begin
            if(PcSrc)
            begin
                instr_out = 32'b00000000000000000000000000000000;
                pc_out =32'b00000000000000000000000000000000;
            end
            else
            begin
                instr_out <= instr_in;
                pc_out <= pc_in;
            end
        end
       
    end
endmodule //ref_if_id